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Question: 1 ee 461g verilog hdl and logic design homework 8...

Question details

1.     EE 461G: Verilog HDL and Logic Design

Homework #8

In this homework, you are given an incompletely specified hierarchical Verilog model with missing modules. Your task is to fill in the missing modules and create a test fixture to test the completed Verilog model.

module hierarchical (data, load, clear, clock, sum, gt, eq, lt);

input [15:0] data;   // 16 bit load for the 16 bit counter.

input load ;            // load the 16-bit data when true.

input clear;             // asynchronous clear for the 16 bit counter

input clock;            // the clock for the 16 bit counter

output [15:0] sum; // the sum of the first 8 bits and second 8-bits of the counter.

output eq;               // true if the first 8 bits is equal to the second 8-bits.

output gt;                // true if the first 8 bits of the counter is greater than the second 8 bits

output lt;                 // true if the first 8 bits of the counter is less than the second 8 bits.

wire [15:0] w;

counter b1 (.data(data), .load(load), .clock(clock), .clear(clear), .q(w));

// this is a 16 bit up counter with load, and asynchronous clear

adder b2 (.a(w[15:8]), .b(w[7:0]), .sum(sum));

compare b3 (.a(w[15:8]), .b(w[7:0]), .lt(lt), .eq(eq), .gt(gt));

endmodule

What to hand in:

1.      A completed hierarchical Verilog HDL model.

2.     A test fixture with sufficient number of input vectors to show that all the features are working.

Simulation output of the design.

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