1. We investigate the increase in CPI (clocks per instruction) due
to cache misses that occur during memory references. For simplicity, we
pretend that instruction fetches never miss.
a) Suppose the processor takes an average of 1.5 clock cycles to
execute an instruction when there are no cache misses. Assume that the miss
penalty is 8 cycles and that there is an average of 1 memory reference per 3
instructions. This _base_ CPI of 1.5 cycles includes the cache hit time.
Suppose the miss rate is 5%. Using the formula t_ave = ht + mr * mp, what
is the CPI when cache misses are taken into account?
b) Consider the same processor with a two-level cache. The hit
rates for the L1$ and the L2$ are 95% and 80%, respectively. The _local_
miss penalties are 8 cycles and 60 cycles, respectively. Assume the same
density of memory references. If the CPI is 1.5 cycles when there are no
cache misses, what is the CPI when cache misses are taken into account?
Hint: Apply the formula recursively to find the effective miss penalty of
the L1$.