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Question: can u please explain how they got the answers for...

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Question 5 (20 points): Answer the following question regarding registers and sequential circuits. a) (10 points) Consider a universal shift register with the functionality shown in the table below Mode control Register operation Parallel Load ν 0 0. Shift left Shift right No Change 0 The registers resets asynchronously to all Os when clear is set Odrrel. All other functions are positive edge triggered. Assume the following inputs: 0 101 inh . Parallel imputs: 1,-0 (left-most bit),lel, A, 1,-i (right-most bit) Serial input for righl-shift0 Serial input for left-shift 1 Assume that the register is initially loaded with all I instances in time, t,.... marked in the following timing diagram? s. What is the register value for the Register value at ty is Register value at t is Register value at t3 is Register value at 4 is Register value at ty is Register value at ts is 010%110
b) (10 points) Modify the circuit diagram below by adding a four-ioput NAND gate to the signals Ay, Ax Ai and Ae and connecting the output of the NAND gate the Reser line. A periodie clock signal is connected to the Count input. Assuming the initial flip-flop state A AyAiAg 1010 when the clock is high, determine the circuit output for these two cases: Without NAND zate With NAND gate · Initial state: . After the next negative clock edge. AA2AAo-4-2-L.L 丄_aㅗㅗ ·After no negative clock edges: AAA宀--し 오요/..1_c . After three negative clock edges: AAA㈥· L오 Afterfour negative clock edges: AAAiA.Lyy10 -Q 으 丄 .Aher /ive negative clock edges: AAAiA.LM-- Your answers should assume that all transients occurring after the clock edge have settled down e. that the output has stabilized to its final value for the clock cycle of interest. 10
Can u please explain how they got the answers for the first part register value at t1 to t6 and for the second part I do not get the part with nand gate.
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