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Question: cda 4253cis 6930 fpga system design assignment 3 1 description...

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CDA 4253/CIS 6930 FPGA System Design Assignment #3 1 Description (1) Design a 4-bit shift register with the following interface specification clock reset din(3:0 load input clock signal input synchronous reset; clear state of the register to all Os data input input when 1, load data din(3:0) in parallel; otherwise, load din(0) serially dout (3:0 outp data outp For this design, create a VHDL model with two different architectures as explained below (a) In one architecture, use a single process statement to describe the design. (b) In another architecture, use 4 process statements plus other necessary statements to de scribe the design. Create a testbench to simulate both models to make sure they are corect. (2) Answer the following question in writing. Suppose the frequency of an available clock is 200 MHz. How would you design a circuit that raises its output for one cycle in every second? (3) (Required for CIS 6930) Design a 8-bit binary-to-BCD converter circuit in (a) combina- tional logic, and (2) sequential logic, and compare their performance & area by reading the implementation reports. The comparison needs to be written up, and submitted along with your designs. 2 Requirements 1. Create a folder hu3-your-name for this assignment, which holds design project files. 2. Create a README file to explain organization of your submission if necessary . For Question 2 and the writing part of Question 3, group all your answers in a file using a text editor e.g. MS-Word . To submit, zip the entire folder hu3-your-name, and upload hu3-your-name.zip file to Can- vas Note: Make sure that your zipped file is in the ZIP format to avoid any potential issues in Note: Make sure that you copy all necessary files into the projects. your original work needs to be eramined. opening your files 5. Make sure that you do NOT modify your work before the HW grading is finished in case that
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