Question: performing a read from a dynamic ram dram requires that...
performing a read from a dynamic RAM (DRAM) requires that the chip precharge before it can supply the requested data. Assume that the precharge takes 10ns and it takes 15ns to output the requested data in response to a read operation or to store the input data for a write operation. Also recall that our MIPS pipeline system employs a Harvard Architecture, transfers 32 bits at a time between the CPU and memory, and each pipeline stage consumes one clock cycle. ⦁
1)If pipeline stages 2, 3, and 5 can each be completed in as little as 5ns, what would be the maximum clock rate (expressed in GHz) that can be used for the pipeline if DDRAM is used for the system memory instead of DRAM (both with the same 10ns precharge time and a 15ns access time)? Recall that DDRAM (double data rate DRAM) performs a transfer on the leading or rising edge of the clock as well as on the trailing or falling edge of the clock.