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Question: please just vhdl code...

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Please just vhdl code.

Leading Zero Detector: This iterative circuit processes a 15-bit input (MSB first) and generates the number of leading 0s before the first 1. Example: v Ifthe sequence is: 000000000011010 → R-10 v If the sequence is: 0001 0000 0011 010 → R-3 v If the sequence is: 0000 0000 1000 001 → R-8 The figure depicts the (in ASM form) and a datapath circuit. Note: Counters. If E-sclr-1,->Q-0 Input data: x (entered sequentially, MSB first). Output data R. Complete the timing diagram of the digital circuit (next page). Note that 3 sequences are evaluated. Write a structural VHDL code. You MUST create a file for i) modulo-(N+1) counter, ii) flip-flop, ii) Finite State Machine, and v) Top file (where you will interconnect all the c Write a testbench according to the timing diagram shown (next page). Simulate the circuit (Behavioral simulation). Verify that the simulation is correct by comparing it with the timing diagram you completed manually Upload the following files to Moodle (an assignment will be created) VHDL code files VHDL testbench x→| LEADING-0 tartDETECTOR start done z S2 scirR start FSM eb er 0 to N counter 0 to N res etn ER ebE ER 1 clock EQ1 EQ← 1 S3 done ← 1

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