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  3. q4 stack design design a stack of depth 7 and...

Question: q4 stack design design a stack of depth 7 and...

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Q4. stack design Design a stack of depth 7 and 8-bit wide - It has two I/O ports, data in[7:0] as input port and data out[7:0] as output port When push signal (active high) is asserted, an 8-bit data entry will be pushed into the stack at the positive edge of the clock if flag full is false (0). Nothing happens if flag full is true - When pop signal (active high) is asserted, an 8-bit data entry will be poped out from the stack at the positive edge of the clock if flag empty is false (0). 8h00 will appear on data-out[ 7:0] if flag empty is true -When clear (active high) is applied, all entries in the stack are cleared, empty is set to 1 and full is set to 0, stack pointer s set to full and empty are both updated at the positive edge of the clock Note: you need a buffer of depth 8 within the stack to store the entries and a stck pointer sp[2:0] pointing to the next empty entry to store the pushed data a stack is empty if sp[2:0] 3b000 a stck is full if sp[2:0]3b11 -each time an entry is pushed to the stack, it takes 2 clock cycles to complete -cycle 1: store the data to buffer (buffer[sp]<-data_in) -cycle 2: increase the stack pointer value by 1, update full and empty flags -each time an entry is poped out from the stack, it takes 2 clock cycles to complete -cycle 1: decrease the stack pointer value by 1 .cycle 2: read buffer[sp] (data outbuffer[sp]); update full and empty flag.s
Depth 7 Stack Module data-in(7:01 data ou 7:0] push elklempty Stack empty Stack full module stack(clk.clear, data_in, push, pop, data_out, full empty); input clk; input clear;/*clear stack if clear 1*/ input [7:0] data in; /* data input port */ input push, pop; /* both active high, push has a higher priority */ output reg [7:0] data out; /*data output port */ output reg full, empty; reg [2:0 sp stack stack pointer */ endmodule
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