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  3. uestion 1 consider a hypothetical harvard architecture computer in which...

Question: uestion 1 consider a hypothetical harvard architecture computer in which...

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uestion 1 Consider a hypothetical Harvard Architecture computer in which all instruc- tions are 16-bit long and the data memory space is byte addressable. (1) Compare the impact on the processor speed between a 8-line data bus and a 16-line data bus for fetching instructions from the program memory space? [3] 2) If the data bus for fetching instructions has 16 lines, what is the maximum volume of program memory space (in KBytes) that can be addressed by a 16- line address bus? [3] (3) If the data bus for fetching instructions has 8 lines instead, what is the minimum number of lines needed for the address bus to cover the same volume of program memory space as (2) 4? (4) Suppose the data memory space is fixed to 8 KBytes in volume, please de- termine the widths for both the data bus and the address bus [3]

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